Recent primary concern for the development of a very large scale integration (VLSI) circuit is to increase a driving current of a metal oxide semiconductor field effect transistor (MOSFET) while reducing power consumption thereof. To meet such requirement, it has been investigated to use a material having higher carrier mobility than silicon as a channel material. Though germanium, gallium-arsenic, and so forth are available as semiconductor materials having high carrier mobility, a practical use of them is yet to be accomplished for the reason that their use addresses thermal safety issues or renders it difficult to form a fine semiconductor/insulator interface, and so forth. Accordingly, it has been attempted to increase the driving current by way of miniaturizing the MOSFET by using silicon as a channel material as it was conventionally, and to reduce power consumption by way of suppressing excessive gate leakage current or short channel effect.
To prevent an excessive increase of the gate leakage current while realizing the miniaturization of the MOSFET, using a gate insulating film having a high dielectric constant is required. Recently, silicon oxynitride (SiON) film having a high dielectric constant is used as a gate insulating film instead of a conventionally employed silicon oxide (SiO2) film. However, improvement of the dielectric constant by the use of the silicon oxynitride film is deemed to have a limit, and a high-k insulating film having a higher dielectric constant is expected to be used as a promising next-generation gate insulating film. To be used for the high-k insulating film, HfO2 or Hf-silicate film is most practical in consideration of a band gap, a dielectric constant and a thermal safety. However, as reported from recent researches, in the event that a poly-Si or metal gate electrode is used on the gate insulating film made of the HfO2 or the Hf-silicate, a work function of the gate electrode varies 2)(Fermi level peening), causing a problem that a threshold voltage cannot be regulated at a desired value. Further, it is also known that carrier mobility deteriorates due to the influence of stationary charges in the insulating film, dipoles generated in an interface layer between the gate electrode and the insulating film, remote phonon scattering, and the like.
As a means to suppress the short channel effect while realizing the miniaturization of the MOSFET, there is known a method of increasing a doping concentration for the channel. However, the increase of the doping concentration would cause an increase of the threshold value over the desired level and a deterioration of the carrier mobility. In consideration of these problems, it is very difficult to enhance the driving capacity by the miniaturization, while concurrently realizing a reduction of the power consumption.
As a structure for improving the driving capacity by suppressing the short channel effect of the MOSFET, there is proposed a double gate structure. The double gate structure refers to a configuration in which a gate insulating film and a gate electrode portion are formed at two opposite thickness-wise surfaces of a semiconductor layer in which a channel is to be formed. The two gates serve to terminate lines of force of electric field from a drain of the MOSFET, and thus prevent an influence of a drain potential upon a source-side end of the channel, whereby the short channel effect is suppressed greatly.
As an actual double gate structure, there is proposed a fin-type field effect transistor (see, for example, Patent References 1 to 5).
In the fin-type field effect transistor, a fin-shaped semiconductor layer is formed on a semiconductor substrate with an insulating film interposed therebetween. A gate insulating film and a gate electrode are formed on both surfaces of the semiconductor layer while the semiconductor layer intervenes therebetween. Since the fin-type field effect transistor has the double gate structure, it can suppress the short channel effect. Accordingly, the doping concentration for the channel can be lowered. As a result, a threshold voltage can be regulated at a desired value, and carrier mobility improves. Furthermore, since channels are formed in the two surfaces, a driving current can be increased. Accordingly, by using a gate insulating film made of HfO2 or Hf-silicate in the fin-type field effect transistor, increase of the driving current and suppression of the gate leakage current and the short channel effect can be all accomplished.
For the manufacture of the fin-type field effect transistor, a SOI wafer capable of reducing off-state leakage current is widely used. The SOI wafer has a laminated structure including a buried oxide layer made of an insulating material and a single crystalline silicon layer formed on a single crystalline substrate wafer. Here, the buried oxide layer is typically formed by a thermal oxidation method.
In the course of manufacturing the fin-type field effect transistor by using the SOI wafer, a fin is generally formed as follows. First, a fin-shaped protrusion is formed on the SOI wafer by performing a dry etching process such as plasma etching on the wafer. Here, the protrusion has a size larger than that of the fin to be finally formed. During the etching process, a damage by plasma or the like is inflicted on the surface of the protrusion.
In the subsequent process, to improve the surface roughness of the fin while narrowing the width thereof, a sacrificial oxide film is formed by oxidizing the surface of the protrusion including the damage and is removed by wet etching which is performed by using hydrofluoric acid or the like. As a result, a fin having a clean surface and a size smaller than that of the first-formed protrusion (a size almost equal to that of the fin to be finally formed) can be obtained.
The method of removing the damage, which is generated by the dry etching, by means of performing the wet etching of the sacrificial oxide film is a simple process. Further, this method enables a formation of a fin having a size that cannot be obtained by using only the dry etching (for example, having a width of about 30 to 40 nm).
However, if the SOI wafer is used as a wafer, that is, in the event that the fin-shaped protrusion is formed on the single crystalline silicon layer on the buried oxide layer by performing the dry etching thereon, and the damage inflicted on the protrusion is removed by the wet etching of the sacrificial oxide film, an undercut 12 would be generated at a base portion of the fin 11 to be formed, as shown in FIG. 4.
The undercut 12 is formed as follows. A top portion of the buried oxide layer 13 that has been exposed by the dry etching is etched together with the sacrificial oxide film when the wet etching of the sacrificial oxide film is performed (the buried oxide layer present before being etched by the wet etching is indicated by a dashed line), and an unexposed portion of the silicon oxide located directly under the fin 11 is partially etched (that is, side etching) due to the isotropy of the wet etching.
If such undercut is generated, residues of gate electrode material or the like would be left in that portion, raising a likelihood of an adverse influence upon a device performance (for example, such a degradation of transistor characteristics as an increase of off current or the like). Though it has been conventionally attempted to remove the residues by cleaning them with a liquid chemical or the like, the cleaning process is complicated, and, besides, it is very difficult to eliminate the residues completely through the cleaning process. Moreover, the presence of the undercut also raises a concern about the strength of the fin because there is a probability that the fin might collapse.
[Patent Reference 1]    Japanese Patent Laid-open Application No. 2003-204068
[Patent Reference 2]    Japanese Patent Laid-open Application No. 2004-128320
[Patent Reference 3]    Japanese Patent Laid-open Application No. 2005-332911
[Patent Reference 4]    U.S. Pat. No. 6,252,284, Specification
[Patent Reference 5]    U.S. Pat. No. 6,413,802, Specification